1. Field of the Invention
The present invention relates to a method and a system for test facilitation designing used to detect failures in an LSI (large-scale integrated circuit) or the like.
2. Description of Related Art
In association with the increase of the complexity and the size of integrated circuits such as the LSI, the DFT (Design For Test) design has become required for generating a test pattern for realizing a high failure detection rate. As one means for the DFT, scan designing is made and ATPG (Automatic Test Pattern Generation) is carried out, thereby making it possible to generate a pattern having a high detection rate. To generate a pattern having higher detection rate, it is required to adopt a DFT method (which is referred to as “test point insertion method” herein) so as to be able to improve circuit controllability and observability.
As the test point insertion method, there are known several methods. As an ordinary method, a pattern is generated by the ATPG and a portion having poor controllability and poor observability (a part a failure of which cannot be detected or of which it is difficult to detect a failure) is identified by a failure simulation. A test circuit is inserted into the identified portion for improving the controllability and observability.
However, with this ordinary method, the part into which a test circuit is inserted is identified after the DFT and ATPG. It is, therefore, required to return to a step before the DFT to insert the test circuit into that part. Such a method requires large-scale iteration, so that the method is not appropriate for a product whose design TAT is short.
One example of background arts is Japanese Patent Application Publication JP-P2000-250946A (referred to as Patent Document 1 in this specification). In the processing flow shown in FIG. 1 in the Patent Document 1, a random pattern is generated to perform a failure simulation. If the failure detection rate of the circuit obtained by the simulation is not sufficiently high, a test point identification processing is performed. The test point is identified as follows. Test point insertion candidates are selected and a test circuit is “hypothetically” inserted into each of the test point candidates. A failure simulation is carried out to see if the detection rate of the circuit improves. If the detection rate improves, the test point insertion candidate is identified as a test point.